1. Field of the Invention
The present invention relates to a power management architecture scheme in a computer system having a plurality of bus masters and at lease one bus slave both being coupled to a system bus. More specifically, the present invention relates to a shadow port and corresponding register used for accessing data, address and status information stored in a plurality of shadow registers pertaining to a most recent input/output ("I/O") bus cycle in order to enable a system management software application to perform its intended purpose.
2. Background of the Field
It is becoming a necessity for many companies to use portable and laptop computers in their daily business activities. As a result, the portable and laptop computer markets are becoming quite profitable and highly competitive within the computer industry. Since portable and laptop computers are becoming more prevalent in the marketplace, there exists a crucial need for efficient power management architecture schemes. This is due to the fact that portable and laptop computers are commonly powered by limited power sources (such as batteries) and thus, power should be conserved wherever possible for reliability and economic reasons.
Conventional power management schemes are generally accomplished by monitoring and controlling power to bus slaves. A bus slave is any type of device that receives, but is incapable of initiating bus cycles, contrary to a bus master which can gain control of the system bus and also initiate bus cycles. Power management is mostly directed toward I/O bus slave devices since such devices generally require a large amount of power to operate in IBM PC/AT compatible computers.
For example, it is commonly known that power must be supplied to an electric motor of a floppy disk drive for the disk drive to operate. However, when the floppy disk drive is not being utilized, the computer system is wasting its limited power supply by unnecessarily powering the disk drive motor. To minimize such waste, a conventional computer system could be designed to discontinue supplying power to the floppy disk drive motor. Unfortunately, such a design would cause its software application to unnecessarily fail if the application sought access to the floppy disk drive which was "powered-off".
In response to the obvious need for effective power management, Intel developed an Intel Architecture Microprocessor 1 comprising a central processing unit ("CPU") 2, a bus controller 3 and a power management macro ("PMM") 4, coupled together by an internal system bus 5 as shown in FIG. 1. The PMM 4 is a special hardware block which provides I/O traps for trapping any access requests by the CPU 2 to any I/O device 9a-9n which has been powered-off and generates a System Management Interrupt ("SMI") signal by activating a SMI control signal line 8 being coupled between the PMM 4 into the CPU 2.
The PMM 4 is capable of generating two kinds of SMIs; namely, a synchronous SMI And an asynchronous SMI. The synchronous SMI occurs due to an internal interrupt, such as a trap, while the asynchronous SMI occurs at any time due to a specific event that requires service before proceeding.
In general, the PMM 4 is used to monitor the computer system for events requiring a change in power status (i.e., whether an I/O device needs to be "powered-off" or "powered-on"). If such an event is detected, the PMM 4 activates the SMI control signal line 8 which acts as a request signal for the CPU 2 to enter into a System Management Mode ("SMM"). SMM is a special mode allowing the CPU 2 to operate in a special environment completely isolated from other software applications. Once the SMM commenced, an internal software service routine, hereinafter referred to as a "SMI handler routine", services the SMI by either powering on or powering off the I/O device. The information necessary to determine whether to "power-on" or "power-off" the I/O device is contained in a SMM status register (not shown) within the PMM 4. After the SMI handler routine has finished servicing the SMI, the SMM would be exited to allow the software application to continue.
The Intel Architecture Microprocessor 1 is coupled to a plurality of bus slaves, preferably I/O devices 9a-9n. All of these devices are coupled together through a peripheral component interconnect bus (the "PCI bus") 6. The CPU 2 incorporated within the Intel Architecture Microprocessor 1 includes a system management first-in last out register (a "SMFILO register") 7 operating in accordance with a first-in, last-out storage scheme. The SMFILO register 7 keeps track of all the I/O cycles generated by the CPU 2. The SMI handler routine reads the SMFILO register 7 and based on the contents thereof, determines which I/O device 9a-9n cannot be accessed, what data was being written, etc. Based on this information, it can decide whether to re-start the I/O bus cycle when the particular I/O device is accessible.
However, one problem associated with the conventional PMM 4 is that it does not manage power consumption for I/O devices being controlled by an alternate bus master 10, but rather, for only I/O devices controlled by the CPU 2. As shown in FIG. 1, the SMFILO register 7 is incorporated within the CPU 2 within the Intel Architecture Microprocessor 1, and thus, the SMFILO register 7 does not store any information pertaining to I/O bus cycles generated by the alternate bus master 10 in the computer system. As a result, if an I/O trap occurs for the alternate bus master 10, the SMI handler routine does not have enough information about to the I/O bus cycle to reliably determine whether to re-start it. Such unreliability has caused many software applications to unnecessarily fail. Moreover, I/O port emulation using traps is not possible for alternate master accesses.